Notched compound semiconductor wafer

ABSTRACT

There is provided a notched compound semiconductor crystal having the same specification even if it is turned over. With respect to a compound semiconductor wafer produced by slicing a compound semiconductor crystal having a crystal plane of (100) plane, the crystal is sliced so as to be tilted from the (100) plane in a direction of [101] or [10−1] when a notch is formed in a direction of [010], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [0−10] or [010] when a notch is formed in a direction of [001], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [001] or [00−1] when a notch is formed in a direction of [0−10], or the crystal is sliced so as to be tilted from the (100) plane in a direction of [010] or [0−10] when a notch is formed in a direction of [00−1].

This application is a 371 of PCT/JP02/05725 filed Jun. 10, 2002.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to a notched compoundsemiconductor wafer. More specifically, the invention relates to anotched compound semiconductor wafer having a plane orientation which istilted in a predetermined direction from the orientation of a crystalplane of a compound semiconductor crystal.

2. Background Art

As semiconductor wafers (which will be hereinafter referred to as“wafers”), such as Si, GaAs and InP wafers, circular wafers are widelyused. As a crystal plane for forming a device, a crystal plane about apredetermined plane orientation, such as a (100), (111) or (511) plane,is usually used. In particular, a wafer having a plane orientationcoming very close to the (100) plane is important.

The ion-implantation or epitaxial growth method is used for forming adevice on the surface of a wafer of GaAs or InP being a typical compoundsemi conductor. As a wafer used for ion-implantation, there is usuallyused a wafer having a plane orientation which has a tolerance of 0.5° orless from the (100) plane. On the other hand, as a wafer used forepitaxial growth, there is often used a wafer having a crystal planewhich is intentionally tilted from the (100) plane in a predeterminedcrystal orientation, since the smoothness of the formed surface of thewafer is important. That is, since there is no atomic step on the just(100) plane in theory, flying material atoms can not find any step edgeswithin a diffusion distance (diffusion length) on the surface, so thatit is difficult to smoothly carry out growth. However, if anatomic stepis formed by intentionally shifting the plane orientation of the waferfrom the (100) plane, material atoms fall in the step within thediffusion length, so that there are some cases where good epitaxialgrowth can be carried out.

FIG. 1 schematically shows the directions of bonds of atoms on the (100)uppermost surface of a compound semiconductor of GaAs as an example of abinary compound semiconductor having a zincblende crystal structure. Asshown in this figure, the dangling bonds on the atomic plane of Gaextend in front and rear directions on the figure, and the danglingbonds on the atomic plane of As extend in right and left directions onthe figure. In addition, the directions of the bonds of Ga atoms areparallel to a [0−1−1] direction, and the directions of the bonds of Asatoms are perpendicular to the [0−1−1] direction. Therefore, the [0−1−1]direction shown in FIG. 1 has different properties from those of a[01−1] direction shown in FIG. 1. Furthermore, throughout thespecification, it is assumed that a negative directional index isexpressed by giving the sign “−” before a number although it isgenerally expressed by giving a bar above a number. Similarly, it isassumed that a coordinate of a lattice plane is expressed by giving thesign “−” before a number when it is negative.

As shown in FIG. 2, if crystal growth proceeds on a step edge, thedirections of bonds on the step edge influence on the crystal growth, sothat a direction in which the plane orientation of a wafer is to betilted is very important. Therefore, a direction (which will behereinafter referred to as an “off direction”), in which the planeorientation of a wafer to be sliced is tilted, defines acrystallographic orientation as a specification of the wafer.

In order to clarify a crystallographic orientation on a plane of awafer, an orientation flat or notch is generally formed in the outerperipheral portion of the wafer. FIG. 3 shows an atomic arrangement ofGaAs when a semiconductor wafer of GaAs having a crystal plane of (100)plane is viewed from the (0−1−1) side assuming that the surface of thewafer is arranged in a [100] direction. From this figure, it can be seenthat the directions of the bonds of atoms on the surface of the waferare different from those on the reverse thereof by 90°. Therefore, atypical compound semiconductor wafer has a secondary flat in addition toa primary orientation flat in order to prevent the surface and reversethereof from being erroneously recognize.

In the case of an Si wafer formed of simple atoms, even if the surfaceof the wafer is mistaken for the reverse thereof before working, thereis no problem since it has no anisotropy. In addition, there is littlepossibility that the surface of the wafer may be mistaken for thereverse thereof since only the device forming surface ismirror-finished. On the other hand, in the case of a compoundsemiconductor wafer, it is more difficult to work the compoundsemiconductor wafer than the case of the Si wafer, and the strength ofthe compound semiconductor wafer is weaker than that of the Si wafer.Therefore, if the compound semiconductor wafer has a diameter of fourinches or more, both sides thereof are generally mirror-finished inorder to meet the demands for higher working precision and strength.

In such circumstances, the position of an orientation flat to be formedin a compound semiconductor wafer having a diameter of four inches orless is standardized. An example of such a standard is SEMI standard9-0999. As shown in FIGS. 4A and 4B, this standard includes a so-calledUS (American) type standard (FIG. 4A) wherein a primary orientation flatis arranged on the (01−1) plane and a secondary orientation flat isarranged on the (011) plane, and a so-called EJ (Euro-Japanese) typestandard (FIG. 4B) wherein a primary orientation flat is arranged on the(0−1−1) plane and a secondary orientation flat is arranged on the (0−11)plane.

In the case of a so-called just wafer which is sliced without beingtilted from the (100) plane, it is sufficient just to conversely workthe surface and reverse of the wafer, so that it is sufficient just tokeep only one kind of sliced wafers as semi-finished products in stockbefore mirror finish.

However, in the case of a wafer which is sliced so as to be tilted fromthe (100) plane in a predetermined direction, there is a problem in thatthe crystallographic orientation in the off direction varies if thewafer is turned over. For example, when a wafer having EJ typeorientation flats is sliced so as to be tilted in a [0−1−1] direction inwhich a primary orientation flat is arranged, i.e., toward the (111)Plane, if the wafer is mistaken for a wafer having US type orientationflats to work the reverse thereof, it is tilted toward the (111) B planewith respect to the primary orientation flat. Referring to FIGS. 5A and5B, this will be described below. FIGS. 5A and 5B show the relationshipbetween the shape of an etch pit on the (100) plane of GaAs due tomolten KOH etching and the crystal orientation. As can be seen fromthese figures, if the wafer is turned over, the direction of the etchpit is shifted by 90° with respect to the primary orientation flat, i.e.the crystallographic orientation is shifted by 90°, and the position ofthe secondary orientation flat is reversed right and left, so that thewafer becomes an absolutely different wafer. Therefore, it is notpossible to cope with the wafer as a just wafer.

Only in a case where the wafer is sliced so as to be tilted in anintermediate direction between the (111) A plane and the (111) B plane,it is possible to obtain a crystallographically equivalent direction.However, there is a problem in that the relative off direction withrespect to the orientation flat is different as shown in FIGS. 6A and6B.

With respect to a wafer having a diameter of six inches, it wasattempted to determine the position of a primary (secondary) orientationflat to define the length of a substantially similar figure, on theextended line of details of a wafer having a diameter of four inches orless. However, since the length of the primary orientation is too long,(1) the balance of the wafer in its rotation during a process is bad,(2) the temperature distribution in the wafer during a heating processis easy to be bad, and (3) the yield of a device deteriorates. In suchcircumstances, it is standardized by SEMI standard M9.7-0200that a notchis provided at a place of the wafer as shown in FIGS. 7A and 7B. In thisstandard, it is standardized that a notch is provided at a position in a[010] direction, not at the crystallographic position of an orientationflat as a conventional notch. That is, since the notch is provided at aposition in an intermediate direction between the (111) A plane and the(111) B plane as shown in FIGS. 7A and 7B, the crystallographicorientations of the notch in front and rear directions and in right andleft directions are not changed even if the wafer is turned over in thecase of the just (100) wafer. This standard has the merits of the factthat it is not required to identify and manage the surface and reverseof a wafer in a working process from a slicing step to a step ofpolishing a mirror-finished surface for forming a device thereon.

However, the above described prior art does not consider the managementof the surface and reverse of a wafer sliced so as to be tilted from the(100) plane, although it can greatly lighten the load on the managementof the surface and reverse of the just (100) wafer. That is, in Table 1and FIG. 3 of SEMI standard M9.7-0200, it is standardized that a waferis sliced so as to be tilted in a [010] direction, in which a notch isto be formed, when the wafer is sliced so as to be tilted in a directionof a group of <110> directions. In this case, as shown in FIGS. 8A and8B, if the wafer is turned over, the off direction is the oppositedirection to the direction of a notch by 180°. That is, the wafer has adifferent specification if the surface of the wafer is mistaken for thereverse thereof.

As described above, since both sides of a wafer having a diameter of sixinches are mirror-polished, it is not easy to identify the surface andreverse of the wafer with the naked eye. Therefore, it is required totake measures to identify the surface and reverse of the wafer during aprocess for working the wafer, and to manage the wafer so that the waferis not turned over. In order to take such measures, a laser marking isprovided on one side of the wafer at the initial stage of the waferworking process. However, since the laser marking disappears during thepolishing of the wafer unless its depth is greater than a margin for thesubsequent working, it is required to deeply dig the laser marking.However, since the wafer has a thickness tolerance (usually ±10 to 20μm), even if the laser marking is so deeply dug, there are problems inthat it is difficult to see a portion for indicating a wafer lot by thelaser marking and that the deeply remaining laser marking causes todamage the wafer.

As another method, there is known a method for asymmetrically chamferingthe outer peripheral portions of a wafer so that the amount of chamberon the side of the surface thereof is different from that on the side ofthe reverse thereof, and for observing the side of the wafer to identifythe surface and reverse of the wafer (see Japanese Patent Laid-Open No.8-195366). However, this method is not always accepted by all customerssince it is easy to depart from the standard shown in FIG. 7 and Tableof SEMI standard M9-0999.

As a further method, there is provided a method for identifying thesurface and reverse of a wafer by asymmetrically chamfering the outerperipheral portions of the wafer so that the amount of chamfer of only anotch portion on the side of the surface thereof is different from thaton the side of the reverse thereof while satisfying the standard of theshape of chamber in the outer peripheral portions (see Japanese PatentLaid-Open No. 2000-331898). This method is promising as a solution.However, since the notch portion is a portion which engages an aligningpin, the slight trouble is that the rate of breakage of wafers increasesin the case of a compound semiconductor, such as GaAs or InP, which iseasily broken.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to eliminate theaforementioned problems and to provide a notched semiconductor waferhaving the same specification at the finishing stage of a final mirrorpolishing process even if any excessive working for identifying thesurface and reverse of the wafer and any complicated management in aprocess are not carried out, i.e., even if the wafer is turned over inthe middle of a process.

In order to accomplish the aforementioned object, the inventors havediligently studied and concluded that the above described problems arecaused by the provision that a compound semiconductor crystal having acrystal plane of (100) plane is sliced so as to be tilted in a [010]direction, in which a notch is to be formed, when the compoundsemiconductor crystal is sliced so as to be tilted from the (100) planein one of a group of <110>directions. Thus, with respect to a compoundsemiconductor wafer produced by sliding a compound semiconductor crystalhaving a crystal plane of (100) plane, the inventors have found that anotched compound semiconductor wafer has the same specification even ifthe wafer is turned over, if the crystal is sliced so as to be tiltedfrom the (100) plane in a [101] or [10−1] direction when a notch isformed in a [010] direction, or if the crystal is sliced so as to betilted from the (100) plane in a [0−10] or [010] direction when a notchis formed in a [001] direction, or if the crystal is sliced so as to betilted from the (100) plane in a [001] or [00−1] when a notch is formedin a [0−10] direction, or if the crystal is sliced so as to be tiltedfrom the (100) plane in a [010] or [0−10] direction when a notch isformed in a [00−1] direction. Thus, the present invention has been made.

That is, a notched semiconductor wafer according to the presentinvention has a plane orientation tilted from the (100) plane in a [101]or [10−1] direction while it has a notch in a [010] direction, or aplane orientation tilted from the (100) plane in a [0−10] or [010]direction while it has a notch in a [001] direction, or a planeorientation tilted from the (100) plane in a [001] or [00−1] directionwhile it has a notch in a [0−10] direction, or a plane orientationtilted from the (100) plane in a [010] or [0−10] direction while it hasa notch in a [00−1] direction.

In the notched compound semiconductor wafer, the angle of the planeorientation to be tilted from the (100) plane is preferably in the rangeof from ±0.5° to 15° . The inplane rotation error in a direction of theplane orientation to be tilted is preferably within ±10°. The notchedcompound semiconductor wafer is preferably made of a compoundsemiconductor having a zincblende crystal structure. The notchedcompound semiconductor wafer is preferably a circular compoundsemiconductor wafer having a diameter of 99.0 mm or more.

In a preferred embodiment of a notched compound semiconductor waferaccording to the present invention, a compound semiconductor wafer to beproduced by slicing a compound semiconductor crystal having a crystalplane of (100) plane is produced by slicing the compound semiconductorcrystal so as to be tilted from the (100) plane in a [101] or [10−1]direction of a group of four crystallographically equivalent <110>directions when a notch is formed in a [010] direction and when thecrystal is sliced so as to be tilted in an intermediate directionbetween the (111) A plane and the (111) B plane. Thus, even if the waferis turned over, it is possible to maintain the working specification ofthe wafer including the positional relationship of the off directionwith respect to the notch. As proposed directions of the notch to beformed in the compound semiconductor wafer produced by slicing thecompound semiconductor crystal having the crystal plane of (100) plane,there are three proposed directions, which are [001], [0−10] and [00−1]directions, in addition to the [010] direction. When the notch is formedin the [001] direction, the crystal is sliced so as to be tilted fromthe (100) plane in the [0−10] or [010] direction. When the notch isformed in the [0−10] direction, the crystal is sliced so as to be tiltedfrom the (100) plane in the [001] or [00−1] direction. When the notch isformed in the [00−1] direction, the crystal is sliced so as to be tiltedfrom the (100) plane in the [010] or [0−10] direction. Also in thesecases, the same advantageous effects can be obtained.

In a preferred embodiment of a notched compound semiconductor waferaccording to the present invention, the angle (which will be hereinafterreferred to as an “off angle”) tilted from the (100) plane is in therange of from 0.5° to 15°. Although about ±0.5° is generally allowed asthe tolerance of the off angle of a wafer, the tolerance of the offangle may be 15° or less so as not to include undesired directions whichare shifted from that in the case of the just (100) water. While thejust (100) wafer has been used as a substrate for ion implantation, amethod for tilting the wafer itself during ion implantation has beencarried out in order to prevent channeling of injected impurities. Inparticular, when ions are injected into the surface of the wafer byscanning beams, not by parallel injection, the wafer often has an offangle of 7 to 10° to ensure uniformity as the diameter of the waferincreases. However, when ions are selectively injected into a portionbeyond a pattern, if the off angle is great, shadow portions are causedto obstruct scale down which will be increasingly required in future. Asmeasures to prevent the shadow of the pattern from being produced in theselectively injected portion, the off angle is set to be 15° or lesssince it is required to carry out a method for tilting the lattice planeon the side of the wafer.

In a preferred embodiment of a notched compound semiconductor waferaccording to the present invention, the inplane rotation error in theoff direction is set to be within ±10°. If the error exceeds this range,the state of elements forming the step edge on the surface of the waferis greatly different from that on the reverse thereof, to influencecharacteristics of an epitaxial growth film. That is, as shown in FIG.9A, when the crystal is sliced so as to be tilted in the just middledirection between the (111) A plane and the (111) B plane, the number ofatoms (shown by ●) having bonds directed toward the step on the stepedge is equal to the number of atoms (shown by ◯) having bonds directedtoward the step on the step edge. However, if the off direction has aninplane rotation error, the number of atoms (shown by ●) directed towardthe step on the step edge is greater than the number of atoms (shown by◯) directed toward the step on the step edge as shown in FIG. 9B. Asdescribed above, on the reverse side in this state, the number of atoms(shown by ◯) having bonds directed toward the step is greater, so thatthe difference between the step states on the surface and reverse sidesis emphasized. In order to avoid this, the inplane rotation error is setto be within ±10°.

A preferred embodiment of a notched compound semiconductor waferaccording to the present invention is made of GaAs, InP or anothercompound semiconductor crystal having a zincblende crystal structure,and has a diameter of four inches or more.

According to the above described preferred embodiment of the presentinvention, a compound semiconductor crystal is sliced so as to be tiltedfrom its crystal plane in a predetermined direction (a predetermineddirection set in accordance with the position of a notch), so that it ispossible to provide a notched semiconductor wafer having the samespecification even if the wafer is turned over. Therefore, it is notrequired to inspect the surface and reverse of the wafer at a polishingstep, so that it is possible to reduce costs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing directions of bonds of atoms onthe (100) uppermost surface of a compound semiconductor of GaAs as anexample of a binary compound semiconductor having a zincblende crystalstructure;

FIG. 2 is a schematic diagram showing the state of crystal growth in astep portion;

FIG. 3 is a schematic diagram showing the atomic arrangement of GaAswhen a semiconductor wafer of GaAs having a crystal plane of (100) planeis viewed from the (0−1−1) side assuming that the surface of the waferis arranged in a [100] direction;

FIGS. 4A and 4B are schematic diagrams showing the position of (primary,secondary) orientation flats standardized by SEMI standard M9-0999;

FIGS. 5A and 5B are schematic diagrams showing the relationship betweenthe shape of an etch pit on the (100) plane of GaAs due to molten KOHetching and the crystal orientation with respect to a wafer which issliced so as to be tilted from the (100) plane of GaAs in apredetermined orientation;

FIGS. 6A and 6B are schematic diagrams showing off directions in US type(FIG. 6A) and EJ type (FIG. 6B) when (primary, secondary) orientationflats are formed at positions standardized by SEMI standard M9-0999 andwhen the off direction is set to be a [100] direction;

FIGS. 7A and 7B are schematic diagrams showing a notch formed at aposition, which is standardized by SEMI standard M9.7-0200, in a waferhaving a crystal plane of (100) plane;

FIGS. 8A and 8B are schematic diagrams showing the relationship betweenthe shape of an etch pit on the (100) plane of GaAs due to molten KOHetching and the crystal orientation with respect to a wafer having anoff direction based on SEMI standard;

FIGS. 9A and 9B are schematic diagrams showing the state of an atomicstep when a compound semiconductor wafer is sliced so as to be tiltedfrom the (100) plane, FIG. 9 A showing the state of anatomic step whenthe wafer is sliced so as to be tilted in the just middle directionbetween the (111) A plane and the (111) B plane, and FIG. 9B showing thestate of an atomic step when the off direction has an inplane rotationerror;

FIG. 10 is a plan view showing the off direction of a wafer and theposition of a notch in Example 1;

FIGS. 11A and 11B are schematic diagrams showing the relationshipbetween the shape of an etch piton the (100) plane of GaAs due to moltenKOH etching and the crystal orientation with respect to a wafer havingthe off direction in Example 1; and

FIGS. 12 and 13 are optical microphotographs on the (100) plane of GaAsdue to molten KOH etching with respect to a wafer having the offdirection in Example 1, the photograph of FIG. 12 corresponding to FIG.11A, and the photograph of FIG. 13 corresponding to FIG. 11B.

DETAILED DESCRIPIOTN OF THE PREFERRED EMBODIMENTS

A notched semiconductor wafer according to the present invention has aplane orientation tilted from the (100) plane in a [101] or [10−1]direction while it has a notch in a [010] direction, or a planeorientation tilted from the (100) plane in a [0−10] or [010] directionwhile it has a notch in a [001] direction, or a plane orientation tiltedfrom the (100) plane in a [001] or [00−1] direction while it has a notchin a [0−10] direction, or a plane orientation tilted from the (100)plane in a [010] or [0−10] direction while it has a notch in a [00−1]direction.

In the notched compound semiconductor wafer, the angle of the planeorientation to be tilted from the (100) plane is preferably in the rangeof from ±0.5° to 15°. The inplane rotation error in a direction of theplane orientation to be tilted is preferably within ±10°. The notchedcompound semiconductor wafer is preferably made of a compoundsemiconductor having a zincblende crystal structure. The notchedcompound semiconductor wafer is preferably a circular compoundsemiconductor wafer having a diameter of 99.0 mm or more.

Examples of notched compound semiconductor wafers according to thepresent invention will be described below in detail.

EXAMPLE 1

Two compound semiconductor wafers 10 of GaAs having a thickness of 800μm and a diameter of six inches were obtained by slicing a compoundsemiconductor crystal of GaAs having a diameter of six inches in adirection tilted by 0.5° from the (100) plane in a [101] direction. Asshown in FIG. 10, in the outer peripheral portion of each of the wafers,a notch 12 was formed in a [010] direction. Then, both sides of each ofthe wafers were polished so that the thickness of each of the wafers was650 μm.

Thereafter, the two wafers were arranged so that the surface and reverseof one of the wafers were opposite to those of the other wafer. Fromeach of the wafers, a light emitting diode (LED) was produced bycarrying out processes, such as epitaxial growth, electrode formationand dice cut. After emission characteristics of the LEDs were examined,there was no problem on emission characteristics of both of the LEDs.Thus, it was verified that the semiconductor wafers obtained in thisexample have the same specification even if they are turned over.

The wafers produced in this example were processed by molten KOH etchingto be observed by an optical microscope. As a result, as shown in FIGS.11A, 11B, 12 and 13, even if the wafers were turned over, the offdirection (left direction in this case) with respect to the notch didnot vary, and the direction of a KOH etch pit did not vary. Thus, it wasfound that the wafers have the same crystallographic and shapespecifications.

EXAMPLE 2

Light emitting diodes (LEDs) were produced by the same method as that inExample 1, except that the slicing direction was a direction tilted by0.5° from the (100) plane in a [10−1] direction. After emissioncharacteristics of the LEDs were examined, there was no problem onemission characteristics of both of the LEDs. Thus, it was verified thatthe semiconductor wafers obtained in this example have the samespecification even if they are turned over. The results of observationby an optical microscope were the same as those in Example 1.

EXAMPLE 3

Two compound semiconductor wafers of GaAs having a thickness of 800 μmand a diameter of six inches were obtained by slicing a compoundsemiconductor crystal of GaAs having a diameter of six inches in adirection tilted by 0.5° from the (100) plane in a [0−10] direction. Inthe outer peripheral portion of each of the wafers, a notch was formedin a [001] direction. Then, both sides of each of the wafers werepolished so that the thickness of each of the wafers was 650 μm.Thereafter, the two wafers were arranged so that the surface and reverseof one of the wafers were opposite to those of the other wafer. Fromeach of the wafers, a light emitting diode (LED) was produced bycarrying out processes, such as epitaxial growth, electrode formationand dice cut. After emission characteristics of the LEDs were examined,there was no problem on emission characteristics of both of the LEDs.Thus, it was verified that the semiconductor wafers obtained in thisexample have the same specification even if they are turned over. Theresults of observation by an optical microscope were the same as thosein Example 1.

EXAMPLE 4

Light emitting diodes (LEDs) were produced by the same method as that inExample 3, except that the slicing direction was a direction tilted by0.5° from the (100) plane in a [010] direction. After emissioncharacteristics of the LEDs were examined, there was no problem onemission characteristics of both of the LEDs. Thus, it was verified thatthe semiconductor wafers obtained in this example have the samespecification even if they are turned over. The results of observationby an optical microscope were the same as those in Example 1.

EXAMPLE 5

Two compound semiconductor wafers of GaAs having a thickness of 800 μmand a diameter of six inches were obtained by slicing a compoundsemiconductor crystal of GaAs having a diameter of six inches in adirection tilted by 0.5° from the (100) plane in a [001] direction. Inthe outer peripheral portion of each of the wafers, a notch was formedin a [0−10] direction. Then, both sides of each of the wafers werepolished so that the thickness of each of the wafers was 650 μm.Thereafter, the two wafers were arranged so that the surface and reverseof one of the wafers were opposite to those of the other wafer. Fromeach of the wafers, a light emitting diode (LED) was produced bycarrying out processes, such as epitaxial growth, electrode formationand dice cut. After emission characteristics of the LEDs were examined,there was no problem on emission characteristics of both of the LEDs.Thus, it was verified that the semiconductor wafers obtained in thisexample have the same specification even if they are turned over. Theresults of observation by an optical microscope were the same as thosein Example 1.

EXAMPLE 6

Light emitting diodes (LEDs) were produced by the same method as that inExample 5, except that the slicing direction was a direction tilted by0.5° from the (100) plane in a [00−1] direction. After emissioncharacteristics of the LEDs were examined, there was no problem onemission characteristics of both of the LEDs. Thus, it was verified thatthe semiconductor wafers obtained in this example have the samespecification even if they are turned over. The results of observationby an optical microscope were the same as those in Example 1.

EXAMPLE 7

Two compound semiconductor wafers of GaAs having a thickness of 800 μmand a diameter of six inches were obtained by slicing a compoundsemiconductor crystal of GaAs having a diameter of six inches in adirection tilted by 0.5° from the (100) plane in a [010] direction. Inthe outer peripheral portion of each of the wafers, a notch was formedin a [00−1] direction. Then, both sides of each of the wafers werepolished so that the thickness of each of the wafers was 650 μm.Thereafter, the two wafers were arranged so that the surface and reverseof one of the wafers were opposite to those of the other wafer. Fromeach of the wafers, a light emitting diode (LED) was produced bycarrying out processes, such as epitaxial growth, electrode formationand dice cut. After emission characteristics of the LEDs were examined,there was no problem on emission characteristics of both of the LEDs.Thus, it was verified that the semiconductor wafers obtained in thisexample have the same specification even if they are turned over. Theresults of observation by an optical microscope were the same as thosein Example 1.

EXAMPLE 8

Light emitting diodes (LEDs) were produced by the same method as that inExample 7, except that the slicing direction was a direction tilted by0.5° from the (100) plane in a [0−10] direction. After emissioncharacteristics of the LEDs were examined, there was no problem onemission characteristics of both of the LEDs. Thus, it was verified thatthe semiconductor wafers obtained in this example have the samespecification even if they are turned over. The results of observationby an optical microscope were the same as those in Example 1.

1. A notched semiconductor wafer which has a plane orientation tiltedfrom a (100) plane in a [101] or [10−1] direction and which has a notchin a [010] direction.
 2. A notched compound semiconductor wafer as setforth in claim 1, wherein an angle of the plane orientation to be tiltedfrom the (100) plane is in the range of from ±0.5° to 15°.
 3. A notchedcompound semiconductor wafer as set forth in claim 1, wherein an inplanerotation error in a direction of the plane orientation to be tilted iswithin ±10°.
 4. A notched compound semiconductor wafer as set forth inclaim 1, which is made of a compound semiconductor having a zincblendecrystal structure.
 5. A notched compound semiconductor wafer as setforth claim 1, which is a circular compound semiconductor wafer having adiameter of 99.0 mm or more.